Optical sensor

ABSTRACT

An amount of charges consonant with the intensity of the light entering photodiodes is generated, and the level of the charges is determined by a charge level determination circuit. Based on this determined charge level, a capacitance setting circuit sets a capacitance of an integrating capacitor unit in an integrating circuit. Thereafter, in the integrating circuit, the charges generated by the photodiodes are integrated in the integrating capacitor unit, and a voltage having a value consonant with the amount of the integrated charges is output. When background light is strong and the overall intensity of incident light is high, a comparatively large capacitance is set for the variable capacitor unit of the integrating circuit, and the intensity of the incident light is detected without saturation. When background light is weak and the overall intensity of incident light is low, a comparatively small capacitance is set for the variable capacitor unit of the integrating circuit, and the intensity of the incident light is detected at high sensitivity, regardless of the surrounding conditions.

TECHNICAL FIELD

[0001] The present invention relates to a light detection apparatus foroutputting a digital signal having a value consonant with the intensityof incident light.

BACKGROUND ART

[0002] A light detection apparatus includes one or more light detectiondevices and an integrating circuit for outputting a voltage having avalue consonant with the amount of electrical charges output by thelight detection devices. In this light detection apparatus, electricalcharges output by the light detection devices, in amounts equivalent tothe intensity of the incident light, are integrated in the integratingcircuit and are output by the integrating circuit as a voltage having avalue consonant with the amount of the integrated charges, and based onthis voltage, the intensity of the incident light is obtained.

[0003] The light detection apparatus may further include an A/Dconverter circuit for converting into a digital signal a voltage (analogsignal) output by the integrating circuit. In this case, the intensityof the incident light can be obtained as a digital value, and can beprocessed by a computer and the like. When multiple light detectiondevices are arranged, either one-dimensionally or two-dimensionally, thelight detection apparatus can be employed as a solid-state image pickupapparatus.

[0004] The CMOS technique can be used to manufacture such a lightdetection apparatus, and when in the integrating circuit the capacitanceof a capacitor for converting a current into a voltage is changed, thedynamic range for the detection of the intensity of the incident lightcan be increased.

[0005] Such a light detection apparatus is disclosed, for example, inreference document “A 32-Channel Charge Readout IC for Programmable,Nonlinear Quantization of Multichannel Detector Data,” S. L. Garverick,et al., IEEE Journal of Solid-State Circuits, Vol. 30, No. 5, pp.533-541 (1995).

[0006] In the same referenced document, the light detection apparatushaving an integrating circuit in which an integrating capacitor unithaving a variable capacitance is provided between the input/outputterminals of an amplifier is shown. The integrating circuit integratesthe charges output by a light detection device in the integratingcapacitor unit, and outputs a voltage having a value consonant with theamount of the integrated charges.

[0007] For the light detection apparatus in this reference, thecapacitance of the integrating capacitor unit is controlled from outsidethe apparatus to increase the dynamic range for the detection of theintensity of the incident light.

[0008] That is, when the capacitance of the integrating capacitor unitis reduced, the detection sensitivity is increased, even when theintensity of the incident light is low. Meanwhile, when the capacitanceof the integrating capacitor unit is increased, saturation of an outputsignal can be avoided, even when the intensity of the incident light ishigh.

[0009] With the light detection apparatus (solid-state image pickupapparatus) described in the above referenced document, even during thedaytime in the middle of summer, for example, when conditions are suchthat the surroundings are brightly lighted, an object can be imagedwithout saturation of an output signal occurring. Further, whenconditions are such that the surroundings are very dark, such as atnight, it is possible to image an object with high sensitivity.

DISCLOSURE OF THE INVENTION

[0010] However, the light detection apparatus described in thereferenced document determines the magnitude of the value of the outputsignal and whether the output signal is saturated, and based on thedetermination results, externally controls the capacitance of theintegrating capacitor unit provided for the integrating circuit. Thus,the light detection apparatus can not rapidly detect the intensity ofincident light.

[0011] Furthermore, when the brightness differs greatly, depending onthe positioning of an object, and when the light detection apparatus (asolid-state image pickup apparatus) described in the above reference isemployed to image, at high sensitivity, a darker portion of an object,saturation of an output signal for the brighter portion of the objectwill occur. Whereas, when the brighter portion of an object is to beimaged to avoid the occurrence of saturation, the imaging sensitivityfor the darker portion of the object is reduced.

[0012] As is described above, for the light detection apparatus(solid-state image pickup apparatus) in the above reference, thecapacitance of the integrating capacitor unit is appropriately set foreach imaging in order to extend the dynamic range for the detection ofthe intensity of the incident light; however, on a screen, the dynamicrange for detecting the intensity of the incident light for each pixelcan not be increased.

[0013] To resolve these problems, it is an objective of the presentinvention to provide a light detection apparatus that can rapidly detectthe intensity of incident light.

[0014] According to the present invention, a light detection apparatuscomprises: a determination circuit for receiving an analog signalconsonant with the output of a light detection device and fordetermining the magnitude of the analog signal; and A/D conversion meansfor converting the analog signal into a digital signal in accordancewith a resolution consonant with the output of the determinationcircuit.

[0015] The resolution of the conversion has a property that is theopposite of the dynamic range. When the light intensity incident to thelight detection device is high, the determination thereof is made by thedetermination circuit, which receives an analog signal consonant withthe output of the light detection device, and A/D conversion isperformed in accordance with the resolution consonant with the output ofthe determination circuit. As a result, even when the resolution isreduced, the dynamic range on the high intensity side is ensured.

[0016] When the intensity of incident light is small, the detectionthereof is made by the determination circuit, and A/D conversion isperformed in accordance with the resolution consonant with the output ofthe determination circuit. As a result, the resolution can be increasedwhile the dynamic range on the high intensity side is narrowed. Ofcourse, since in this case the intensity of the incident light is low,essentially, the A/D conversion may not be performed on the highintensity side.

[0017] Especially, since an analog signal in consonance with the outputof the light detection device is entered, the A/D conversion means forreceiving this analog signal can be controlled by the determinationcircuit that has received the analog signal. Since the resolution of theA/D conversion means is not controlled based on the luminance of adigitized video signal unlike in the conventional case, high-speedcontrol is possible.

[0018] There are several possible configurations for this A/D conversionmeans.

[0019] According to one of these configurations, the A/D conversionmeans includes: an integrating circuit, in which a group of capacitorsconnected to the rear stage of the light detection device is connectedin parallel between the input/output terminals of the operationalamplifier; and a capacitance setting circuit for, before integrating ofcharges in the capacitor group is started, setting, in accordance withthe output of the determination circuit, a combined capacitance of thegroup of capacitors between the input/output terminals.

[0020] Generally, a relationship is established wherein a voltage=theamount of charges/a capacitance. Therefore, when there is an increase inthe combined capacitance as the intensity of the incident light isincreased, the change in the voltage output by the integrating circuit,relative to the change in the amount of charges, is reduced, as is theconversion resolution; however, even when the intensity of the incidentlight is high, the intensity of the incident light can be detectedwithout the output voltage becoming saturated. Whereas, when thecombined capacitance is reduced as the intensity of the incident lightis lowered, the change in the output voltage of the integrating circuit,relative to the change in the amount of charges, is increased, as is theconversion resolution.

[0021] As another configuration, the A/D conversion means comprises: (A)an integrating circuit connected to the rear stage of a light detectiondevice; and (B) an A/D converter circuit, including a main capacitor forintegrating charges proportional to the output of the integratingcircuit, multiple sub-capacitors for integrating the charges that aretransferred from the main capacitor in which the charges have beenintegrated, and a capacitance controller for controlling the transfer ofcharges to the multiple sub-capacitors, and for outputting the controlvalue as the digital signal, wherein the amount of charges that can beintegrated in each of the sub-capacitors is set in accordance with theoutput of the determination circuit. In this case, the A/D convertercircuit adjusts the resolution based on the output of the determinationcircuit.

[0022] In this case, when a voltage applied at both ends of each of thesub-capacitors is decided depending on the output of the determinationcircuit, the amount of charges that can be integrated in each of thesub-capacitors is set.

[0023] As still another configuration, the A/D conversion meanscomprises: (1) an integrating circuit connected to the rear stage of thelight detection device; and (2) an A/D converter circuit including, amain capacitor for integrating charges proportional to the output of theintegrating circuit, multiple sub-capacitors for integrating the chargesthat are transferred from the main capacitor in which the charges havebeen integrated, and a capacitance controller for controlling thetransfer of the charges to the multiple sub-capacitors, and foroutputting as the digital signal a value for controlling, wherein agroup of sub-capacitors having a specific group of capacitances isselected from among the sub-capacitors in accordance with the output ofthe determination circuit, and wherein charges are transferred from themain capacitor to the selected group of sub-capacitors under the controlof the capacitance controller.

[0024] Furthermore, there is a conceivable configuration in which thechange amount of an analog signal from the light detection device isincreased, regardless of the performance of A/D conversion. In thiscase, a light detection apparatus comprises: (1) a light detectiondevice for generating and outputting an amount of charges correspondingto the intensity of incident light; (2) an integrating circuit,including an integrating capacitor unit having a variable capacitance,for integrating charges generated by the light detection device in theintegrating capacitor unit, and for outputting a voltage correspondingto the amount of the integrated charges; (3) a charge leveldetermination circuit for determining the level of the charges generatedby the light detection device; and (4) a capacitance setting circuit forsetting a capacitance for the integrating capacitor unit based on thecharge level determined by the charge level determination circuit,before a charge accumulation operation by the integrating circuit isstarted.

[0025] According to this light detection apparatus, an amount of chargesconsonant with the intensity of the light entering the light detectiondevice is generated, and the level of the charges is determined by thecharge level determination circuit. Based on the determined chargelevel, the capacitance setting circuit sets the capacitance of theintegrating capacitor unit in the integrating circuit.

[0026] Thereafter, in the integrating circuit, the charges generated bythe light detection device are integrated in the integrating capacitorunit, and a voltage consonant with the amount of the integrated chargesis output. When the intensity of incident light is high, a comparativelylarge value is set for the capacitance of the variable capacitor unit inthe integrating circuit. Since the output voltage=the amount ofcharges/the capacitance, the change in the voltage relative to thechange in the amount of charges is reduced, and when the A/D conversionis performed for the output of the integrating circuit, the resolutionis lowered, but the intensity of incident light, even when it is high,can be detected without saturation.

[0027] On the other hand, when the intensity of incident light is low, acomparatively small value is set for the capacitance of the variablecapacitor unit in the integrating circuit, the change in the voltagerelative to the change in the amount of charges is increased, and theintensity of incident light, even when it is low, can be detected at ahigh resolution, i.e., with high sensitivity.

[0028] According to the present invention, the light detection apparatusfurther comprises: an A/D converter circuit for performing the A/Dconversion of a voltage output by the integrating circuit, and foroutputting a digital signal. In this case, the voltage output by theintegrating circuit is input to the A/D converter circuit, whichconverts the voltage into a digital signal and outputs this digitalsignal.

[0029] Further, according to the present invention, the light detectionapparatus additionally comprises: a shift circuit for receiving adigital signal output from the A/D converter circuit, and for shiftingbits of the digital signal, in accordance with the charge leveldetermined by the charge level determination circuit to output theresultant signal. In this case, the digital signal output by the A/Dconverter circuit is output following the shifting of the bits by theshift circuit in accordance with the charge level determined by thecharge level determination circuit.

[0030] Furthermore, according to the light detection apparatus of thepresent invention, (1) the capacitance of the integrating capacitor unitcan be set to a first capacitance or a second capacitance, and the firstcapacitance is 2^(n) times (n is an integer equal to or greater thanone) the second capacitance, and (2) the A/D converter circuit outputs adigital signal having n or greater bits. In this case, the digitalsignal output by the A/D converter circuit is subject to n-bit leftshift, as needed, and the value of the obtained digital signalrepresents a superior linearity relative to the intensity of incidentlight.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031]FIG. 1 is a schematic diagram showing a configuration of a lightdetection apparatus 1 according to the present embodiment;

[0032]FIG. 2 is a circuit diagram showing an integrating circuit 10, acharge level determination circuit 20 and a capacitance setting circuit30 in the light detection apparatus 1 according to the presentembodiment;

[0033]FIG. 3A is a circuit diagram showing a shift circuit 200 in thelight detection apparatus 1 according to the present embodiment;

[0034]FIGS. 3B and 3C are diagrams showing two patterns for a digitalsignal output by the shift circuit 200;

[0035]FIGS. 4A to 4L are timing charts for explaining the operation ofthe light detection apparatus 1 according to the present embodiment;

[0036]FIG. 5 is a graph showing the relationship between the value of a12-bit digital signal, output by the shift circuit 200 of the lightdetection apparatus 1 according to the embodiment, and the intensity ofincident light;

[0037]FIG. 6 is a schematic diagram showing the configuration of a lightdetection apparatus 1 according to another embodiment;

[0038]FIG. 7 is a circuit diagram showing an integrating circuit 10, adetermination circuit 20 and a capacitance setting circuit 30 in thelight detection apparatus 1 according to the present embodiment;

[0039]FIG. 8 is a circuit diagram showing an A/D converter circuit 40;

[0040]FIG. 9 is a circuit diagram showing another A/D converter circuit40;

[0041]FIG. 10A is a timing chart showing the opening/closing of a switchSW110; and

[0042]FIG. 10B is a timing chart showing the opening/closing of a switchSW120.

BEST MODES FOR CARRYING OUT THE INVENTION

[0043] The embodiments of the present invention will now be described indetail while referring to the accompanying drawings. For the explanationof the drawings, the same reference numerals are employed to denotecorresponding components to avoid overlapping during the explanation.

[0044]FIG. 1 is a schematic diagram showing the configuration of a lightdetection apparatus 1 according to the present embodiment. This lightdetection apparatus 1 includes: M units (M is an integer equal to orgreater than two) 100 ₁ to 100 _(M), a shift circuit 200 and a controlcircuit 300. These M units 100 ₁ to 100 _(M) have the same configurationto one another, and each includes a plurality of photodiodes (lightdetection devices) PD, switches SW, an integrating circuit 10, a chargelevel determination circuit 20, a capacitance setting circuit 30, an A/Dconverter circuit 40 and switches SW₅₁ and SW₅₂.

[0045] For the photodiodes PD of each unit 100 _(m) (m is an arbitraryinteger equal to or greater than one and equal to or smaller than M),the anode terminals are grounded, while the cathode terminals areconnected to the input end of the integrating circuit 10, via theswitches SW, and are also grounded through capacitors Cd. The capacitorsCd may be junction capacitors for the photodiodes PD, or may be providedseparately from the photodiodes PD.

[0046] When the switches connected to the cathode terminals are opened,the photodiodes PD generate an amount of charges consonant with theintensity of incident light and accumulate these charges in a capacitorCv. When the switches are closed, the photodiodes PD output the chargesintegrated in the capacitor Cv to the integrating circuit 10 and thecharge level determination circuit 20. It should be noted that Cv inFIG. 1 is a capacitor provided to the wiring connected to the input endof the integrating circuit 10.

[0047] The integrating circuit 10 of each unit 100 _(m) includes anintegrating capacitor unit having a variable capacitance. Theintegrating circuit 10 integrates, in the integrating capacitor unit,charges generated by the photodiodes PD, and outputs to the A/Dconverter circuit 40 a voltage consonant with the amount of integratedcharges. The charge level determination circuit 20 of each unit 100 _(m)determines the amount (level) of the charges generated by eachphotodiode PD, and outputs a charge level signal Level, representing thedetermination results, to the capacitance setting circuit 30 as well asto the shift circuit 200 through the switch SW₅₂.

[0048] The capacitance setting circuit 30 in each unit 100 _(m) receivesthe charge level signal Level output from the charge level determinationcircuit 20, and before the charge accumulation operation of theintegrating circuit 10 is initiated, the capacitance setting circuit 30sets a capacitance for the integrating capacitor unit of the integratingcircuit 10 based on the charge level signal Level. The A/D convertercircuit 40 of each unit 100 _(m) receives a voltage output from theintegrating circuit 10, performs the A/D conversion of this voltage toobtain a digital signal, and transmits the digital signal to the shiftcircuit 200 through the switch SW₅₁.

[0049] The shift circuit 200 sequentially receives, through the switchSW₅₁, the digital signals output from the A/D converter circuit 40 ineach unit 100 _(m), and in addition, sequentially receives, through theswitch SW₅₂, the charge level signal Level from the charge leveldetermination circuit 20 in each unit 100 _(m). Then, the shift circuit200 shifts the bits of the digital signal in accordance with the valueof the charge level signal Level, and outputs the resultant digitalsignal.

[0050] The control circuit 300 controls the entire operation of thelight detection apparatus 1, and outputs control signals for controllingthe opening/closing of the switches SW connected to the photodiodes PD,the switch SW₅₁, the switch SW₅₂, and the internal switches of theintegrating circuit 10 and the like. It should be noted that in FIG. 1control signals transmitted by the control circuit 300 to the othercomponent circuits are not shown.

[0051] Next, the individual component circuits will be described indetail.

[0052]FIG. 2 is a circuit diagram showing the integrating circuit 10,the charge level determination circuit 20 and the capacitance settingcircuit 30 of the light detection apparatus 1 according to the presentembodiment.

[0053] The integrating circuit 10 of each unit 100 _(m) includes anamplifier A₁₀, switches SW₁₀ to SW₁₃, capacitors Cf₁₁ and Cf₁₂ and an ORcircuit 11. The inverted input terminal of the amplifier A₁₀ isconnected to the input end of the integrating circuit 10 through theswitch SW₁₃, a constant voltage V_(inp) is applied to the uninvertedinput terminal, and the output terminal is connected to the output endof the integrating circuit 10.

[0054] The switch SW₁₀ is provided between the inverted input terminaland the output terminal of the amplifier A₁₀. The switch SW₁₁ and thecapacitor Cf₁₁ are connected in series, and are provided between theinverted input terminal and the output terminal of the amplifier A₁₀.Similarly, the switch SW₁₂ and the capacitor Cf₁₂ are connected inseries and are provided between the inverted input terminal and theoutput terminal of the amplifier A₁₀. The capacitance of the capacitorCf₁₁ is greater than the capacitance of the capacitor Cf₁₂.

[0055] The switch SW₁₀ is opened or closed based on a first reset signalReset1 output by the control circuit 300, and the switches SW₁₁ and SW₁₂are opened or closed based on a control signal output by the capacitancesetting circuit 30. The OR circuit 11 receives a second reset signalReset2 and an integration start signal Start from the control circuit300 and outputs a logical sum of these two logic signals. Then, switchSW₁₃ performs opening/closing based on the logic signal output by the ORcircuit 11.

[0056] In the integrating circuit 10, the switches SW₁₁ and SW₁₂ and thecapacitors Cf₁₁ and Cf₁₂ constitute a variable capacitor unit having avariable capacitance. That is, as any of the switches SW₁₁ and SW₁₂ isclosed, a value of a feedback capacitance between the inverted inputterminal and the output terminal is the capacitance values any of thecapacitor Cf₁₁ and of the capacitor Cf₁₂.

[0057] The charge level determination circuit 20 of each unit 100 _(m)includes a comparator circuit 21, a logic inversion circuit 22 and NANDcircuits 23 and 24. The inverted input terminal of the comparatorcircuit 21 is connected to the input end of the charge leveldetermination circuit 20, and a reference voltage V_(ref) is applied tothe uninverted input terminal. The comparator circuit 21 compares thepotential at the input end of the charge level determination circuit 20with the reference voltage V_(ref). Then, when the potential at theinput end of the charge level determination circuit 20 is higher thanthe reference voltage V_(ref), the comparator circuit 21 outputs a logicsignal at a logic level L to the output terminal, whereas when thepotential is not higher, the comparator circuit 21 outputs a logicsignal at a logic level H to the output terminal. The logic inversioncircuit 22 receives from the control circuit 300 the first reset signalReset1, inverts the logic of this signal, and outputs the inverted logicsignal. While to set the reference voltage V_(ref) applied to theuninverted input terminal of the comparator circuit 21, the followingequation is used:

V _(ref)=(Cf ₁₂ ·V _(sat))/(Cd+Cv)  (1)

[0058] In this equation, V_(sat) defines the saturation voltage at whichan amount of charges sufficient to saturate the capacitor Cf₁₂ isintegrated, the capacitor Cf₁₂ having the small capacitance.

[0059] The NAND circuit 23 receives logic signals output from thecomparator circuit 21 and the NAND circuit 24, inverts the logicalproduct of these two logic signals and outputs the inverted signal. TheNAND circuit 24 receives logic signals output from the logic inversioncircuit 22 and the NAND circuit 23, inverts the logical product of thesetwo logic signals and outputs the inverted signal. That is, the NANDcircuits 23 and 24 latch a logic signal output from the comparatorcircuit 21. Thus, the charge level determination circuit 20 determinesthe level of the charges generated by each photodiode PD, and the NANDcircuit 24 outputs the charge level signal Level as the determinationresults.

[0060] The capacitance setting circuit 30 in each unit 100 _(m) includesa logic inversion circuit 31 and OR circuits 32 and 33.

[0061] The logic inversion circuit 31 receives the charge level signalLevel output by the charge level determination circuit 20, inverts thissignal and outputs the inverted signal.

[0062] The OR circuit 32 receives the second reset signal Reset2 outputby the control circuit 300, and the charge level signal Level output bythe charge level determination circuit 20, and outputs the logical sumof these two logic signals.

[0063] The OR circuit 33 receives the second reset signal Reset2 outputby the control circuit 300 and the logic signal output by the logicinversion circuit 31, and outputs the logical sum of these two logicsignals.

[0064] The switch SW₁₁ of the integrating circuit 10 is opened or closedbased on the logic signal output by the OR circuit 32 of the capacitancesetting circuit 30, and the switch SW₁₂ of the integrating circuit 10 isopened or closed based on the logic signal output by the OR circuit 33of the capacitance setting circuit 30.

[0065]FIG. 3A is a circuit diagram showing the shift circuit 200 of thelight detection apparatus 1 according to the embodiment, and FIGS. 3Band 3C are diagrams showing two patterns for a digital signal output bythe shift circuit 200. Hereinafter, the capacitance of the capacitorCf₁₁ in the integrating circuit 10 of each unit 100 _(m) is defined as16 (=2⁴) times the capacitance of the capacitor Cf₁₂. The A/D convertercircuit 40 in each unit 100 _(m) outputs 8-bit digital signals D₇ to D₀.

[0066] The shift circuit 200 includes 12 selectors, 201 to 212. Each ofthese selectors 201 to 212 includes input terminals A and B, as well asa terminal for receiving the charge level signal Level output by thecharge level determination circuit 20. When the charge level signalLevel is at logic level H, each of the selectors 201 to 212 outputs tothe output terminal the logic level input at the input terminal A.Whereas when the charge level signal Level is at logic level L, each ofthe selectors 201 to 212 outputs to the output terminal the logic levelinput at the input terminal B.

[0067] The selector 201 receives at the input terminal A logic level L,and receives at the input terminal B the least significant bit D₀ of an8-bit digital signal output by the A/D converter circuit 40.

[0068] The selector 202 receives at the input terminal A the logic levelL, and receives at the input terminal B bit D₁ of the 8-bit digitalsignal output by the A/D converter circuit 40.

[0069] The selector 203 receives at the input terminal A the logic levelL, and receives at the input terminal B bit D₂ of the 8-bit digitalsignal output by the A/D converter circuit 40.

[0070] The selector 204 receives at the input terminal A the logic levelL, and receives at the input terminal B bit D₃ of the 8-bit digitalsignal output by the A/D converter circuit 40.

[0071] The selector 205 receives at the input terminal A the leastsignificant bit D₀ of the 8-bit digital signal output by the A/Dconverter circuit 40, and receives at the input terminal B bit D₄.

[0072] The selector 206 receives at the input terminal A bit D₁ of the8-bit digital signal output by the A/D converter circuit 40, andreceives at the input terminal B bit D₅.

[0073] The selector 207 receives at the input terminal A bit D₂ of the8-bit digital signal output by the A/D converter circuit 40, andreceives at the input terminal B bit D₆.

[0074] The selector 208 receives at the input terminal A bit D₃ of the8-bit digital signal output by the A/D converter circuit 40, andreceives at the input terminal B the most significant bit D₇.

[0075] The selector 209 receives at the input terminal A bit D₄ of the8-bit digital signal output by the A/D converter circuit 40, andreceives at the input terminal B a logic level L.

[0076] The selector 210 receives at the input terminal A bit D₅ of the8-bit digital signal output by the A/D converter circuit 40, andreceives at the input terminal B the logic level L.

[0077] The selector 211 receives at the input terminal A bit D₆ of the8-bit digital signal output by the A/D converter circuit 40, andreceives at the input terminal B the logic level L.

[0078] The selector 212 receives at the input terminal A bit D₇ of the8-bit digital signal output by the A/D converter circuit 40, andreceives at the input terminal B the logic level L.

[0079] That is, when the charge level signal Level output by the chargelevel determination circuit 20 is at the logic level H, the shiftcircuit 200, which has the twelve selectors 201 to 212, outputs adigital signal of 12 bits (D₇, D₆, D₅, D₄, D₃, D₂, D₁, D₀, 0, 0, 0, 0)(FIG. 3B).

[0080] Whereas, when the charge level signal Level is at the logic levelL, the shift circuit 200 outputs a digital signal of 12 bits (0, 0, 0,0, D₇, D₆, D₅, D₄, D₃, D₂, D₁, D₀) (FIG. 3C).

[0081] As is described above, the shift circuit 200 receives a digitalsignal of 8 bits output by the A/D converter circuit 40, and when thecharge level signal Level is at the logic level H, the shift circuit 200performs 4-bit left shift to the digital signal, the 4-bit beingconsonant with the ratio 16 (=2⁴) of the capacitances of the capacitorsCf₁₁ and Cf₁₂ of the integrating circuit 10, and outputs a digitalsignal of 12 bits.

[0082] The operation of the light detection apparatus 1 according tothis embodiment will now be described. FIGS. 4A to 4L are timing chartsfor explaining the operation of the light detection apparatus 1according to this embodiment.

[0083] Before time t1, the first reset signal Reset1, the second resetsignal Reset2 and the integration start signal Start, which are outputby the control circuit 300, are at logic level L (FIGS. 4A to 4C). Allthe switches SW connected to the photodiodes PD are open (FIG. 4D).

[0084] At time t1, the first reset signal Reset1 and the second resetsignal Reset2 output by the control circuit 300 go to logic level H(FIGS. 4A and 4B). Then, the logic signal output by the OR circuit 11 ofthe integrating circuit 10 goes to logic level H, and the logic signalsoutput by the OR circuits 32 and 33 of the capacitance setting circuit30 also go to the logic level H. Thereafter, the switches SW₁₀ to SW₁₂in the integrating circuit 10 are closed, the capacitors Cf₁₁ and Cf₁₂are discharged, and the capacitors Cf₁₁ and Cf₁₂ are initialized (FIGS.4E to 4G). In addition, the switch SW₁₃ in the integrating circuit 10 isclosed, and the potential of the wiring, for the connection in common ofthe switches connected to the photodiodes PD, becomes a constant voltageV_(inp) applied to the uninverted input terminal of the amplifier A₁₀ inthe integrating circuit 10. Furthermore, the constant voltage V_(inp) isapplied to the input end of the charge level determination circuit 20(FIG. 4H).

[0085] Subsequently, at time t2, the second reset signal Reset2 goes tologic level L, and the switch SW₁₃ of the integrating circuit 10 isopened (FIG. 4H). At time t3, the first reset signal Reset1 goes tologic level L, and the switch SW₁₀ in the integrating circuit 10 isopened to enable the performance of the integral operation by theintegrating circuit 10 (FIG. 4E).

[0086] At time t4, the switch SW connected to any one of the photodiodes PD is closed. Thus, the value of the input signal to the chargelevel determination circuit 20 is changed from the current voltageV_(inp) to voltage V_(video), which is represented by the followingequation (FIG. 4I).

V _(video)=(I _(sh) ·T _(int))/(Cd+Cv)  (2)

[0087] In this equation, I_(sh) defines the magnitude of a photocurrentflowing in the photodiode PD in accordance with the intensity ofincident light, T_(int) defines a period during which the switch SWconnected to the photodiode PD is opened, and a product I_(sh)·T_(int)defines the amount of charges integrated in the capacitor Cd during theperiod T_(int). In the charge level determination circuit 20, thecomparator circuit 21 compares the above input signal voltage V_(video)with the reference voltage V_(ref), and determines the level of thecharges generated by the photodiode PD. Then, the NAND circuits 23 and24 latch the comparison results, and the NAND circuit 24 outputs thecharge level signal Level that represents the determination results ofthe level of the charges generated by the photodiode PD (FIG. 4J).

[0088] If the intensity of incident light is high and the input signalvoltage V_(video) of the charge level determination circuit 20 is lowerthan the reference voltage V_(ref), the logic signal output by thecomparator circuit 21 goes to the logic level H, and the charge levelsignal Level goes to the logic level H. The logic signal output by theOR circuit 32 of the capacitance setting circuit 30 also goes to thelogic level H, and the switch SW₁₁ of the integrating circuit 10 isclosed.

[0089] The logic signal output by the OR circuit 33 of the capacitancesetting circuit 30 goes to logic level L, and the switch SW₁₂ of theintegrating circuit 10 is opened. Thus, the capacitance of theintegrating capacitor unit in the integrating circuit 10 is thecomparatively large capacitance of the capacitor Cf₁₁. Then, at time t5,the integration start signal Start, output by the control circuit 300,once goes to logic level H and then falls to logic level L.

[0090] Therefore, the switch SW₁₃ in the integrating circuit 10 is onceclosed and is then opened. When the switch SW₁₃ is closed, the capacitorCf₁₁ integrates the amount (I_(sh)·T_(int)) of charges generated, inconsonance with the intensity of the incident light, by the photodiodePD, and the voltage V_(c) output by the integrating circuit 10 isrepresented by the following equation (FIG. 4K).

V _(c)=(I _(sh) ·T _(int))/Cf ₁₁  (3)

[0091] Then, the voltage V_(c) converted into a digital signal (D₇ toD₀) by the A/D converter circuit 40.

[0092] When, however, the intensity of the incident light is low and theinput signal voltage V_(video) to the charge level determination circuit20 is higher than the reference voltage V_(ref), the logic signal outputby the comparator circuit 21 goes to logic level L, and the charge levelsignal Level goes to the logic level L. At this time the logic signaloutput by the OR circuit 32 of the capacitance setting circuit 30 alsogoes to logic level L, and the switch SW₁₁ of the integrating circuit 10is opened. Furthermore, the logic signal output by the OR circuit 33 ofthe capacitance setting circuit 30 goes to logic level H, and the switchSW₁₂ of the integrating circuit 10 is closed. Therefore, the integratingcapacitor unit of the integrating circuit 10 has the comparatively smallcapacitance of Cf₁₂. At time t5, the integration start signal Start,output by the control circuit 300, once goes to logic level H, and thento logic level L. Thus, the switch SW₁₃ in the integrating circuit 10 isonce closed and then opened. When the switch SW₁₃ is closed, thecapacitor Cf₁₂ integrates the amount (I_(sh)·T_(int)) of chargesgenerated by the photodiode PD, in consonance with the intensity of theincident light, and the voltage V_(c) output by the integrating circuit10 is represented by the following equation.

V _(c)=(I _(sh) ·T _(int))/Cf ₁₂  (4)

[0093] Then, the voltage V_(c) is converted into digital signal (D₇ toD₀) by the A/D converter circuit 40.

[0094] The above described operation is performed in parallel by theunits 100 ₁ to 100 _(M). Thereafter, under the control of the controlcircuit 300, the switches SW₅₁ and SW₅₂ in each unit 100 _(m) aresequentially closed, and the digital signals (D₇ to D₀) output by theA/D converter circuit 40 and the charge level signal Level output by thecharge level determination circuit 20 are input to the shift circuit200. When the charge level signal Level is at logic level H, the 8-bitdigital signal input to the shift circuit 200 is subject to 4-bit leftshift, and a digital signal of 12 bits (D₇, D₆, D₅, D₄, D₃, D₂, D₁, D₀,0, 0, 0, 0) is output (FIG. 4L). Whereas when the charge level signalLevel is at logical level L, 4 digits of 0 are added preceding the upperbit of the 8-bit digital signal input to the shift circuit 200, and adigital signal of 12 bits (0, 0, 0, 0, D₇, D₆, D₅, D₄, D₃, D₂, D₁, D₀)is output by the shift circuit 20.

[0095]FIG. 5 is a graph showing a relationship between the value of a12-bit digital signal, output by the shift circuit 200 of the lightdetection apparatus 1 according to this embodiment, and the intensity ofthe incident light. When the input signal voltage V_(video) of thecharge level determination circuit 20 is higher than the referencevoltage V_(ref), i.e., when the charge level signal Level is at logiclevel H, the capacitance of the variable capacitor unit of theintegrating circuit 10 is the comparatively large capacitance Cf₁₁, andthe intensity of the incident light, even when it is high, can bedetected without saturation. Whereas, when the input signal voltageV_(video) of the charge level determination circuit 20 is lower than thereference voltage V_(ref), i.e., when the charge level signal Level isat logic level L, the capacitance of the variable capacitor unit of theintegrating circuit 10 is the comparatively small capacitance of thecapacitor Cf₁₂, and the intensity of the incident light, even when it islow, can be sensitively detected.

[0096] As is described above, since the light detection apparatus 1according to this embodiment can appropriately and quickly set thecapacitance of the variable capacitor unit of the integrating circuit 10for each photodiode PD, a large dynamic range is obtained for thedetection of the intensity of the incident light for each pixel, and theintensity of the incident light can be detected at high speed.

[0097] For the light detection apparatus 1 according to this embodiment,it is assumed that the capacitance of the capacitor Cf₁₁ in theintegrating circuit 10 is 16 (=2⁴) times the capacitance of thecapacitor Cf₁₂, the A/D converter circuit 40 outputs a digital signal of8 bits, and the shift circuit 200 performs 4-bit left shift to thedigital signal, as needed. Generally, it is preferable that thecapacitance of the capacitor Cf₁₁ of the integrating circuit 10 be 2^(n)times (n is an integer equal to or greater than one) the capacitance ofthe capacitor Cf₁₂, that the A/D converter circuit 40 output a digitalsignal equal to or greater than n bits, and that the shift circuit 200perform n-bit left shift to the digital signal as needed.

[0098] Thus, the value of the digital signal output by the shift circuit200 represents an excellent linearity relative to the intensity of theincident light.

[0099] This embodiment can be variously modified. For example, differentmode of structures can be employed for the individual componentcircuits. The specific circuit structure for the variable capacitor unitof the integrating circuit 10 is especially not limited to the one forthe above embodiment, and a different circuit structure can also beemployed. The capacitance available for the variable capacitor unit ofthe integrating circuit 10 is not limited to two levels, as in thisembodiment, and three or more levels may be used. Further, the chargelevel determination circuit 20 and the capacitance setting circuit 30can be appropriately configured in accordance with the number of thelevels.

[0100] The shift circuit 200 is not always necessary. A data processingapparatus, such as a computer, may receive a digital signal output fromthe A/D converter circuit 40 and a charge level signal Level output fromthe charge level determination circuit 20, and may thereafter perform arequired process.

[0101] The A/D converter circuit 40 is also not always necessaryprovided. The data processing apparatus may perform an A/D conversionfor an input voltage output from the integrating circuit 10, may alsoreceive a charge level signal Level output from the charge leveldetermination circuit 20 and may perform thereafter a necessary process.

[0102] According to the light detection apparatus 1 of this embodiment,included in each of M (M is an integer equal to or greater than two)units, 100 ₁ to 100 _(M), is a plurality of two-dimensionally arrangedphotodiodes PD that enables the imaging of two-dimensional images.However, M=1 may be employed instead, and a plurality of photodiodes PDmay be arranged one-dimensionally for the imaging of one-dimensionalimages. Further, M=1 and a single photodiode PD may be included, andinstead of imaging an object, the intensity of incident light may simplybe detected. Also in this case, a large dynamic range may be obtainedfor the detection of the intensity of incident light, which can then bedetected quickly, even when the intensity of incident light is greatlyor rapidly changed.

[0103] As is described above, the light detection apparatus includes:the determination circuit 20 for receiving an analog signal (voltage)from the integrating circuit 10 in accordance with the output of thelight detection device PD; and A/D conversion means 10 and 40 forconverting, into a digital signal, the analog signal that is input at aresolution consonant with the output of the determination circuit 20.The analog signal can be input to the determination circuit 20 inaccordance with the output of the light detection device PD, and basedon this signal, the A/D conversion can be performed by the internalcontrol of the A/D conversion means 10 and 40. Thus, unlike in theconventional case, the resolution of the A/D conversion means is notcontrolled based on the luminance of a digitized video signal, so that arapid control process can be performed.

[0104] In this embodiment, the A/D conversion means includes: theintegrating circuit 10, in which the group of the capacitors Cf₁₁ andCf₁₂, connected to the rear stage of the light detection device PD, areconnected in parallel between the input/output terminals of theoperational amplifier A₁₀; and the capacitance setting circuit forsetting, in accordance with the output of the determination circuit 20,the combined capacitance of the group of the capacitors Cf₁₁ and Cf₁₂,located between the input/output terminals of the operational amplifierA₁₀, before starting the operation of charge accumulation in thecapacitor group Cf₁₁ and Cf₁₂, wherein the dynamic range can be changedquickly, as is described above.

[0105] Generally, the voltage=the amount of charges/the capacitance isestablished. Therefore, when the combined capacitance is increased asthe intensity of the incident light is heightened, the change in theoutput voltage of the integrating circuit is reduced, relative to thechange in the amount of charges, and the resolution for conversion isdiminished, while the intensity of the incident light, even when it ishigh, can be detected without saturation of the output voltage. On theother hand, when the combined capacitance is reduced as the intensity ofincident light is lessened, the change in the output voltage of theintegrating circuit is increased, relative to the change in the amountof charges, and the resolution for conversion is enhanced.

[0106]FIG. 6 is a schematic diagram showing the configuration of a lightdetection apparatus 1 according to another embodiment. The lightdetection apparatus 1 of this embodiment differs, in the following twopoints, from the light detection apparatus of the previous embodiment.The first difference is that in this embodiment the capacitance of anintegrating circuit 10 is not variable. The second difference is that,while the capacitance of the integrating circuit 10 is fixed, the A/Dconversion resolution and the dynamic range of an A/D converter circuit40 are complementarily variable, and are set in accordance with theoutput of a charge level determination circuit 20. Detailed descriptionwill be made below.

[0107] For the light detection apparatus of this embodiment, as well asfor that of the previous embodiment, the integrating circuit 10 inputsan analog signal (voltage) to the A/D converter circuit 40, inaccordance with the output of a light detection device PD, and thedetermination circuit 20 determines the magnitude of an analog outputthat is consonant with the output of the light detection device. A/Dconversion means 10 and 40 convert into a digital signal an analogsignal inputted at a resolution consonant with the output of thedetermination circuit 20.

[0108] The resolution of an A/D conversion has a characteristic oppositeto that of the dynamic range of an A/D conversion. That is, to convertinto a digital signal an analog signal having a predetermined rangemagnitude, the resolution is high when a small predetermined range canbe set. However, when a capacitor is employed for A/D conversion, theratio of the change in the voltage to the change in the amount ofcharges is proportional to the reciprocal of the capacitance. Therefore,in other words, when a capacitor that can accumulate a small amount ofcharges is employed, the resolution can be increased. On the other hand,since only a small amount of charges can be integrated, the dynamicrange is narrowed. In order to increase the amount of charges to beintegrated, either only the voltage applied at both ends of thecapacitor must be increased or only the capacitance itself must beincreased.

[0109] When the intensity of the light entering the light detectiondevice PD is high, detection thereof is made by the determinationcircuit 20 for receiving an analog signal consonant with the output ofthe light detection device, and the A/D conversion is performed at aresolution consonant with the output of the determination circuit 20. Asa result, on the high intensity side, the dynamic range is ensured evenwhen the resolution is reduced.

[0110] Further, when the intensity of the light entering the lightdetection device PD is reduced, detection thereof is made by thedetermination circuit 20, and an A/D conversion is performed at aresolution consonant with the output of the determination circuit 20. Asa result, the resolution can be increased while the dynamic range on thehigh intensity side is narrowed. Of course, in this case, sinceessentially the intensity of the incident light is reduced, the A/Dconversion may not be performed on the high intensity side.

[0111] As in the previous embodiment, an analog signal is transmitted tothe determination circuit 20 in accordance with the output of the lightdetection device PD, and the A/D conversion is performed based on theoutput of the determination circuit 20. Unlike in the conventional case,however, in this process control of the resolution of the A/D conversionmeans is not based on the luminance of a digitized video signal, andhigh-speed control can be exercised.

[0112]FIG. 7 is a circuit diagram showing the integrating circuit 10,the determination circuit 20 and a capacitance setting circuit 30 in thelight detection apparatus 1 according to this embodiment. In thisconfiguration, the light detection apparatus 1 according to thisembodiment differs from the apparatus shown in FIG. 2 only in that theoutput of the determination circuit 20 is transmitted not to theintegrating circuit 10, but to the A/D converter circuit 40 at thesucceeding stage. Since the integrating circuit 10 does not employ theoutput of the determination circuit 20, unlike the one shown in FIG. 2,only one capacitor Cf₁₂ is provided. Of course, a plurality ofcapacitors may be provided.

[0113] The level of a voltage output by the capacitance setting circuit30 is changed at a predetermined value of the intensity of the incidentlight detected by the light detection device PD. In this embodiment, byusing this signal switching, the amount of charges to be integrated bythe capacitor of the A/D converter circuit 40 at the succeeding stage ischanged, and the resolution and the dynamic range of the A/D conversionare altered. As is described above, in order to increase the amount ofcharges to be integrated by the capacitor, either only the voltageapplied at both ends of the capacitor or only the capacitance itselfmust be increased. First, a description will be made of theconfiguration employed for increasing the voltage applied at both endsof the capacitor.

[0114]FIG. 8 is a circuit diagram showing the A/D converter circuit 40.An analog signal (voltage) is output by the integrating circuit 10,through a capacitor 40X, to the inverted input terminal of anoperational amplifier 40A. A main capacitor Cmain is located between theinput/output terminals of the operational amplifier 40A, and an amountof charges consonant with the magnitude of an analog signal isintegrated. It should be noted that the charges integrated in the maincapacitor are reset by closing a switch SWC for short-circuiting themain capacitor Cmain.

[0115] A voltage consonant with the charges integrated by the maincapacitor Cmain is generated at the output terminal of the operationalamplifier 40A and is input to a comparator 40B. When the amount ofcharges integrated in the main capacitor Cmain is reduced to be lessthan a predetermined value, the absolute value of the voltage input tothe comparator 40B becomes smaller than a standard voltage Vcom, so thatthe output voltage of the comparator 40B goes to level L (or level H,depending on the setting). Until the output voltage of the comparator40B reaches level L, a capacitance controller 40C controls to changeswitches SW₁₁₁ to SW₁₁₄, or switches SW₁₂₁ to SW₁₂₄, and transfers thecharges integrated in the main capacitor Cmain to a group ofsub-capacitors C_(S111) to C_(S114), or C_(S121) to C_(S124). In thisembodiment, the sub-capacitor groups C_(S111) to C_(S114) and C_(S121)to C_(S124) have the same configuration, including their capacitances,and either group of sub-capacitors can serve as a substitute for theother group.

[0116] For example, when the switch SW₁₁₁ is connected to a referencevoltage Vref2, a part of the charges integrated in the main capacitorCmain is transferred to the sub-capacitor C_(S114), the voltage input tothe comparator 40B is reduced and one bit is set to “1”. Further, inorder to set the lower bits, the switch SW₁₁₂ is connected to thereference voltage Vref2, and at this time, when the voltage input to thecomparator 40B falls below a predetermined value as a result of thetransfer of charges from the main capacitor Cmain, the capacitancecontroller 40C disconnects the switch SW₁₁₂ and sets this bit to “0.”When the switching is thereinafter controlled in the same manner, thiscontrol value is proportional to the magnitude of an analog signal, sothat the control value itself is output as a digital signal from thecapacitance controller 40C. The capacitances of each capacitor are setto be 2^(n) times one another.

[0117] During the A/D conversion operation, first, charges integrated inthe main capacitor Cmain are discharged by closing the switch SWC, andthereafter, charges proportional to the analog signal (voltage) from theintegrating circuit 10 are integrated by the main capacitor Cmain. Thedetermination circuit 20 inputs to the switches SW₁₁₀ and SW₁₂₀ aninstruction indicating whether the reference voltage Vref1 or thereference voltage Vref2 should be employed. Instruction signals S1 andS2, output by the determination circuit 20 and the capacitance settingcircuit 30 for designating the reference voltage that should be used,depend on the intensity of the light entering the light detection devicePD. Here, it is assumed that S1 is at level H when the intensity of theincident light is high, that S2 is at level H when the intensity of theincident light is low, and that accordingly, either switch SW₁₁₀ orSW₁₂₀ is connected.

[0118] In short, when the intensity of incident light is high, thesub-capacitor group C_(S111) to C_(S114) can be connected to thereference voltage Vref2, and when the intensity of incident light islow, the sub-capacitor group C_(S121) to C_(S124) can be connected tothe reference voltage Vref1. When the reference voltage is higher, morecharges can be integrated in the connected capacitors, thus thereference voltage Vref2, used when the intensity of incident light ishigh, is higher than the reference voltage Vref1. It should be notedthat no charges are integrated when both ends of a capacitor areconnected to the same voltage Vcom.

[0119] In this embodiment, the A/D conversion means includes: (1) theintegrating circuit 10 to be connected to the succeeding stage of thelight detection devices PD; and (2) the A/D converter circuit thatincludes the main capacitor Cmain, where charges proportional to theoutput of the integrating circuit 10 are integrated, multiplesub-capacitors C_(S111), C_(S112), C_(S113) and C_(S114) (C_(S121),C_(S122), C_(S123) and C_(S124)), where charges are transferred from themain capacitor Cmain and are integrated, and the capacitance controller40C, for controlling the transfer of charges to the multiplesub-capacitors C_(S111), C_(S112), C_(S113) and C_(S114) (C_(S121),C_(S122), C_(S123) and C_(S124)), and for outputting the control valueas a digital signal.

[0120] In accordance with the output of the determination circuit 20,the amount of accumulable charges is set for the sub-capacitorsC_(S111), C_(S112), C_(S113) and C_(S114) (C_(S121), C_(S122), C_(S123)and C_(S124)) (in this embodiment, the reference voltage is set). Inother words, since the amount of charges=the capacitance×the voltage,when the voltage at both ends of each of the sub-capacitors C_(S111),C_(S112), C_(S113) and C_(S114) (C_(S121), C_(S122), C_(S123) andC_(S124)) is controlled, the amount of accumulable charges is changed,and the resolution and the dynamic range are changed. In this case,unlike in the preceding embodiment, the A/D converter circuit adjuststhe resolution based on the output of the determination circuit 20.

[0121] In this embodiment, the voltage applied at both ends of each ofthe sub-capacitors C_(S111), C_(S112), C_(S113) and C_(S114) (C_(S121),C_(S122), C_(S123) and C_(S124)) is determined depending on the outputof the determination circuit 20, and the amount of accumulable chargesis set for each of the sub-capacitors C_(S111), C_(S112), C_(S113) andC_(S114) (C_(S121), C_(S122), C_(S123) and C_(S124)).

[0122] That is, when the switch SW₁₁₀ is closed by the output S1 fromthe determination circuit 20, the group of sub-capacitors C_(S111),C_(S112), C_(S113) and C_(S114) can be connected to the referencevoltage Vref2 by the control of the capacitance controller 30. In otherwords, the amount of charges accumulable for each capacitor isdetermined in accordance with the reference voltage Vref2.

[0123] Similarly, when the switch SW₁₂₀ is closed by the S2 output fromthe determination circuit 20, the group of sub-capacitors C_(S121),C_(S122), C_(S123) and C_(S124) can be connected to the referencevoltage Vref1 by the control of the capacitance controller 30. In short,the amount of accumulable charges is determined by selecting thereference voltage Vref1.

[0124] Then, whether charges are to be integrated in these capacitors,i.e., whether charges should be transferred from the main capacitorCmain, need only be determined by the capacitance controller 40C in theabove described manner, so that the A/D conversion can be performed.

[0125]FIGS. 10A and 10B are timing charts showing the opening andclosing of the switches SW₁₁₀ and SW₁₂₀. For example, when the intensityof the incident light is high, from time t1 to t2 the switches SW₁₁₀ andSW₁₂₀ are closed and then opened, and following time t3 the switch S110is closed, so that the reference voltage Vref2 can be employed. When thereference voltage Vref can be employed, charges can be integrated in thegroup of the sub-capacitors C_(S111), C_(S112), C_(S113) and C_(S114) inaccordance with a difference from the reference voltage Vref, and theA/D conversion can be performed with a wide dynamic range.

[0126] On the other hand, when the intensity of the incident light islow, charges can be integrated in the group of the sub-capacitorsC_(S121), C_(S122), C_(S123) and C_(S124) by enabling the use of thereference voltage Vref1, and the A/D conversion can be performed at ahigh resolution.

[0127] In the above, the amount of accumulable charges has beencontrolled by controlling the reference voltage. However, a plurality ofcapacitors may be employed and the amount of charges may be controlledby changing the capacitances of these capacitors.

[0128]FIG. 9 is a circuit diagram showing another A/D converter circuit40.

[0129] In this case, the A/D conversion means includes: (1) theintegrating circuit 10 to be connected to the succeeding stage of thelight detection devices PD; and (2) the A/D converter circuit, whichincludes the main capacitor Cmain, whereby charges proportional to theoutput of the integrating circuit 10 are integrated, a plurality ofsub-capacitors C_(S111), C_(S112), C_(S113) and C_(S114) (C_(S121),C_(S122), C_(S123) and C_(S124)), where charges are transferred from themain capacitor Cmain and are integrated, and the capacitance controller40C for controlling the transfer of charges to the multiplesub-capacitors and for outputting the control value as a digital signal,wherein, from among the multiple sub-capacitors, a capacitor group(e.g., C_(S111), C_(S112), C_(S113) and C_(S114)) of a specificcapacitance group is selected, in accordance with the output of thedetermination circuit 20, and charges are transferred from the maincapacitor Cmain to the selected capacitor group by the control of thecapacitance controller 40C.

[0130] The circuit in FIG. 9 differs from the circuit in FIG. 8 in onlytwo points: the reference voltages Vref1 and Vref2 are replaced by asingle reference voltage Vref, and the capacitances of thesub-capacitors differ. When the capacitances of the capacitors C_(S111),C_(S112), C_(S113) and C_(S114) in FIG. 8 are defined as Cp, (Cp/2),(Cp/4) and (Cp/8), the capacitances of the capacitors C_(S121),C_(S122), C_(S123) and C_(S124) are Cq, (Cq/2), (Cq/4) and (Cq/8),respectively. That is, Cp and Cq are different values, and it should benoted that Cp>Cq.

[0131] The operation of the circuit in FIG. 9 is the same as that inFIG. 8. When one of sub-capacitor groups is selected for use, thecapacitances Cp and Cq, which are the base capacitances for thesub-capacitor groups, are switched in the same manner as when thereference voltages Vref1 and Vref2 are switched.

[0132] Further, as described for the circuit in FIG. 8, when theintensity of incident light is high, from time t1 to t2 the switchesSW₁₁₀ and SW₁₂₀ are closed and then opened, and following t3, the switchSw₁₁₀ is closed to permit the use of the group of the sub-capacitorsC_(S111), C_(S112), C_(S113) and C_(S114), which have the basecapacitance Cp. Since a large amount of charges can be integrated in thegroup of the sub-capacitors C_(S111), C_(S112), C_(S113) and C_(S114),the A/D conversion can be performed with a wide dynamic range.

[0133] When the intensity of incident light is low, following t3 theswitch SW₁₂₀ is closed to permit the use of the group of thesub-capacitors C_(S121), C_(S122), C_(S123) and C_(S124), which have thebase capacitance Cq. Since only a small amount of charges can beintegrated in the sub-capacitors C_(S111), C_(S112), C_(S113) andC_(S114), the A/D conversion can be performed at a high resolution. Itshould be noted that the relationship between the intensity of incidentlight and the digital output of the shift circuit 200 is the same asthat shown in FIG. 5.

[0134] Industrial Applicability

[0135] The present invention can be used for a light detectionapparatus.

1. (Deleted)
 2. (Amended) A light detection apparatus comprising: adetermination circuit for receiving an analog signal consonant withcharges output by a light detection device and for determining themagnitude of said analog signal; an integrating circuit, in which agroup of capacitors connected to the rear stage of said light detectiondevice is connected in parallel between the input/output terminals ofoperational amplifier; and a capacitance setting circuit for setting,before accumulation of charges in said group of capacitors is started,in accordance with the output of the determination circuit, a combinedcapacitance for the group of capacitors connected between theinput/output terminals, so that a dynamic range is set for an outputvoltage of said integrating circuit, wherein A/D conversion is performedfor said output voltage.
 3. (Amended) The light detection apparatusaccording to claim 2, further comprising: an A/D converter circuit forconverting the output of said integrating circuit into a digital signal.4. The light detection apparatus according to claim 3, furthercomprising: a shift circuit for receiving a digital signal output fromsaid A/D converter circuit, and for shifting bits of said digitalsignal, in accordance with the output of said determination circuit tooutput the resultant signal.
 5. The light detection apparatus accordingto claim 3, wherein said combined capacitance can be set to a firstcapacitance or a second capacitance, and said first capacitance is 2^(n)times (n is an integer equal to or greater than one) said secondcapacitance, and wherein said A/D converter circuit outputs a digitalsignal having n or greater bits.
 6. (Amended) A light detectionapparatus comprising: a determination circuit for receiving an analogsignal consonant with the output of a light detection device and fordetermining the magnitude of said analog signal; and A/D conversionmeans for converting said analog signal into a digital signal inaccordance with a resolution consonant with the output of saiddetermination circuit, wherein said A/D conversion means includes anintegrating circuit connected to the rear stage of the light detectiondevice, and an A/D converter circuit, having a main capacitor forintegrating charges proportional to the output of the integratingcircuit, multiple sub-capacitors for integrating said charges that aretransferred from the main capacitor in which said charges have beenintegrated, and a capacitance controller for controlling the transfer ofsaid charges to said multiple sub-capacitors, and for outputting thecontrol value as the digital signal, and wherein the amount of chargesaccumulable in each of said sub-capacitors is set in accordance with theoutput of said determination circuit.
 7. The light detection apparatusaccording to claim 6, wherein a voltage applied to both ends of each ofsaid sub-capacitors is determined depending on the output of saiddetermination circuit, and the amount of charges accumulable in each ofsaid sub-capacitors is set.
 8. (Amended) A light detection apparatuscomprising: a determination circuit for receiving an analog signalconsonant with the output of a light detection device and fordetermining the magnitude of said analog signal; and A/D conversionmeans for converting said analog signal into a digital signal inaccordance with a resolution consonant with the output of saiddetermination circuit, wherein said A/D conversion means includes anintegrating circuit connected to the rear stage of said light detectiondevice, and an A/D converter circuit having a main capacitor forintegrating charges proportional to the output of said integratingcircuit, multiple sub-capacitors for integrating said charges that aretransferred from said main capacitor in which said charges have beenintegrated, and a capacitance controller for controlling the transfer ofsaid charges to said multiple sub-capacitors, and for outputting thecontrol value as the digital signal, wherein a group of sub-capacitorshaving a specific group of capacitances is selected from among saidmultiple sub-capacitors in accordance with the output of saiddetermination circuit, and wherein charges are transferred from saidmain capacitor to said selected group of sub-capacitors under thecontrol of said capacitance controller.
 9. (Deleted)
 10. (Deleted)